Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Senior Principal STA Physical Design Engineer at Astera Labs driving RTL-to-GDS design of connectivity ASICs for AI infrastructure, ensuring signoff across synthesis, place-and-route, STA, and formal verification using Cadence/Synopsys toolchains.
Owns and improves Astera Labs' internal platforms for manufacturing data, hardware test infrastructure, test automation, and failure analysis. Day-to-day work centers on Python-based data pipelines, Linux/cloud services, CI/CD, and observability tools used by engineering and manufacturing teams.
An Analog/Mixed-Signal IC Design Engineer at Astera Labs designs and verifies advanced-node CMOS circuits (PLLs, DLLs, ADCs, regulators, amplifiers, TX/RX, CDRs) for AI infrastructure connectivity products using tools like Spectre and MATLAB.
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