SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
Designs and deploys AI capabilities—models, APIs, tools, and integrations—for U.S. federal agencies, working with product, research, infrastructure, and legal teams. Uses Python and frontier AI models to build production-grade SDKs, APIs, and developer tools for government missions.
Designs digital ASICs and FPGAs for SpaceX's Starshield national-security programs, writing RTL in Verilog/System Verilog and taking designs through verification, timing closure, and silicon bring-up for space and ground infrastructure.
Leads a team of cybersecurity engineers defending SpaceX's Starshield satellite network, running red-team exercises, vulnerability discovery, and incident response. Hands-on role blending software and security; requires a Top Secret clearance.
Leads digital ASIC/FPGA design verification for Starlink chips, owning test plans from start to finish and supporting pre-silicon verification through post-silicon validation, using UVM/OVM/VMM methodologies and Python scripting.
Leads digital ASIC and FPGA verification for SpaceX’s next-generation Starlink chips, owning test plans from development through pre-silicon verification, chip bring-up, and post-silicon validation using UVM/OVM/VMM, constrained random verification, and Python scripting.
Principal Design Verification Engineer for SpaceX's Starlink silicon team, leading digital ASIC/FPGA verification at block and system level, developing test plans, coverage models, and performing pre-silicon verification, chip bring-up, and post-silicon validation using UVM, constrained random verification, Python, and RTL design.
Principal Electrical Design Engineer at SpaceX Starlink designing, developing, and testing high-reliability electronics for satellite communication gateways and customer hardware (user terminals, routers), owning full lifecycle from concept through production using mixed-signal design, FPGAs, high-speed interfaces, and Python/C++.
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