Senior Hardware Reliability Engineer for SpaceX's Starshield program, troubleshooting satellite hardware failures, performing root cause analysis on PCBAs, and collaborating with cross-functional teams to improve reliability and yield using electrical test equipment and reliability engineering processes.
Ensures reliability and quality of Starlink Aviation hardware (phased-array, Wi-Fi, harnessing, power supply PCBAs) through design, manufacturing, test, and fleet support. Runs reliability tests, investigates failures, drives corrective actions, and improves production processes.
Designs Starlink consumer hardware from concept through high-volume production, including the factory production lines and automation that build it, using CAD/FEA, mechanical and electromechanical design, testing, and manufacturing at SpaceX's Bastrop, TX facility.
The Sr. PCB Designer creates PCB layouts for SpaceX's in-house Starshield board designs, partnering with hardware engineers on stackup, placement, routing, libraries, and fabrication documentation using ECAD tools such as Mentor Xpedition and Altium Designer.
A Sr. PCB Designer at SpaceX creates PCB layouts (2–20+ layers) for Starlink hardware such as radio phased arrays and power converters, partnering with hardware engineers on placement, routing, signal/power integrity, and fabrication documentation.
Senior PCB Designer on SpaceX's Starship team responsible for multilayer PCB layout, component placement, high-speed routing, SI/PI simulations, and fabrication deliverables, collaborating with hardware engineers and using tools like Altium and Xpedition.
The Sr. Physical Security Hardware Specialist installs, maintains, troubleshoots, and repairs security infrastructure including access control, CCTV, and video management systems across SpaceX facilities. The role involves hardware fabrication, inventory management, user training, and collaboration with Lenel and Avigilon system administrators.
Installs, maintains, troubleshoots, and repairs physical security hardware—including CCTV, access control, and intrusion systems—across SpaceX facilities, working with Lenel and Avigilon platforms and supporting system users.
Designs, analyzes, and tests high-power DC-DC converters and electrical power systems for SpaceX’s Starmind satellites and orbital AI data centers, handling magnetics, control loops, and harsh-environment hardware from 1W to many kW.
Designs, analyzes, and tests DC-DC power converters and electrical power systems for Starlink satellites and ground hardware, working with cross-functional teams on power conversion from 1W to kilowatts in harsh environments.
Senior Power Electronics Engineer for Starship who rapidly develops high-reliability rocket and spacecraft electronics, driving DC-DC power converter and power distribution design from requirements and schematic capture through prototyping, bring-up, testing, and manufacturing.
Leads design of kilovolt-level power supplies and DC-DC converters for SpaceX Starlink traveling wave tube amplifiers, owning hardware from concept through production and collaborating with RF, mechanical, and manufacturing teams.
Sr. RFIC Design Engineer designing cutting-edge RF/analog/mixed-signal ICs for Starlink satellite and ground systems, using SiGe/CMOS processes and microwave frequencies (Ku/K/Ka-band).
Sr. RFIC Design Engineer at SpaceX designing next-gen RFICs for Starlink satellite internet, working on SiGe/CMOS circuits at microwave frequencies (Ku/K/Ka-band), simulating with Spectre/ADS/HFSS, and collaborating across systems, firmware, and validation teams.
Designs, simulates, and models RF/analog/mixed-signal integrated circuits for SpaceX's Starlink satellite and ground systems, working with cross-disciplinary teams on next-generation RFICs using SiGe or CMOS processes.
Develops next-generation Starlink silicon, handling physical implementation from synthesis through signoff (floorplanning, place and route, timing, power/ground grid, physical verification) and improving design flows with automation scripts, working with ASIC teams on timing, power, and area targets. Core technologies: ASIC/SOC RTL2GDSII, EDA tools, STA, Python/TCL/Perl scripting.
Designs and implements next-generation ASIC/SOC silicon for SpaceX's Starlink satellite and ground infrastructure. Day-to-day work includes physical implementation (synthesis, floorplanning, place-and-route, timing, signoff), flow automation, and collaboration with architecture and design teams.
Designs and implements next-generation silicon chips for SpaceX's Starlink network, managing physical design flows from synthesis through signoff using EDA tools and scripting. Collaborates with cross-disciplinary teams on timing, power, area, and physical verification for space and ground infrastructure.
Senior software engineer building test automation infrastructure for Starshield satellites, developing Python/C++ software for hardware-in-the-loop testbeds, production floor automation, and data analysis across digital/analog interfaces (CAN, SPI, I2C, RF). Requires US person status for ITAR.
Leads a team of reliability technicians performing root cause analysis on Starlink hardware electrical systems and PCBAs, owns day-to-day production root cause lab operations, and drives reliability and manufacturing quality improvements with design and manufacturing teams.
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