Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads customer engagements for Astera Labs' Scorpio PCIe switches, guiding hyperscalers and AI system builders from design-in through production deployment. Owns lab bring-up, debug, and system-level integration of high-speed connectivity silicon (PCIe Gen 6/7, UALink, UCIe), while authoring technical collateral and mentoring junior applications engineers.
Designs and implements complex digital blocks for AI connectivity silicon, owning blocks from micro-architecture through RTL and silicon bring-up. Works with PCIe, CXL, Ethernet, DDR and advanced CMOS nodes (≤7nm) using Cadence/Synopsys flows, while mentoring engineers and collaborating with verification and physical design teams.
Leads physical design timing closure for Astera Labs' connectivity ASICs, owning end-to-end static timing analysis (STA) from RTL through sign-off. Works fully on-site in Toronto with RTL, physical design, and verification teams using Cadence/Synopsys tools at TSMC 7nm and below.
As a Hardware Validation Engineer for our Data Center Engineering Labs, you will bridge the gap between traditional data center facilities operations and Research and Development systems engineering. Based in our…
Directs hardware product engineering for Nex Playground, an active-play consumer device, owning end-to-end development from concept through global-scale manufacturing, leading engineers, managing ODM/JDM partnerships, and driving compliance and quality for family entertainment hardware.
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