Senior Mechanical Design Engineer at Anduril Industries who owns end-to-end mechanical hardware design—from concept through prototyping and volume manufacturing—for autonomous air, sea, ground, and strike platforms. Works with CAD (SolidWorks, NX, Creo), ASME Y14.5 GD&T, FEA, and fabrication processes like CNC machining and composites.
Designs, builds, and tests complex electro-mechanical systems—including PCBs, motors/actuation, and control systems—at Anduril's Costa Mesa HQ, leading hardware prototypes from concept through production with high autonomy.
Designs printed circuit boards for Anduril's defense products, working with engineers to create high-reliability assemblies using Altium Designer. Implements high-speed digital, RF, analog, and power designs while managing component libraries, IPC standards, and coordination with fab and assembly houses.
Designs printed circuit boards end-to-end for Anduril's defense products in Reston, Virginia—handling requirements, schematics, component selection, layout, bring-up, and testing—using Altium Designer across high-speed digital, analog, RF, and power electronics.
Designs and lays out printed circuit boards for avionics test systems used in development, qualification, verification, and validation. Partners with avionics, system, and software engineers using Altium, applying high-speed digital, controlled-impedance, signal-integrity, and power-integrity best practices.
The engineer owns power regulation and DC-DC conversion for maritime autonomous vehicles, designing voltage regulation circuits, optimizing efficiency and thermal performance in sealed enclosures, and supporting EMI/EMC and prototype testing. Core technologies include power electronics, voltage regulation, EMI/EMC, and marine power systems.
Designs, simulates, tests, and optimizes RF and mixed-signal circuits and subsystems for defense systems, handling component selection, schematics, PCB layout guidance, bench testing with VNAs and spectrum analyzers, and simulation in Ansys and AWR Microwave Office; U.S. Secret clearance eligibility required.
Manages development programs for Anduril's Air Dominance & Strike division, owning cost, schedule, and integration of autonomous aircraft and missile technologies with the Chief Engineer and U.S. Department of Defense customers.
Manages warehouse and material operations at Anduril Industries, a defense technology company. Day to day, the role leads a warehouse team, oversees inventory accuracy and KPIs, implements SOPs and ERP/WMS systems, and ensures compliance with aerospace/defense regulations and safety standards.
Senior Modem SOC Design Engineer at Blue Origin, designing digital hardware for the TeraWave satellite communications SOC, owning RTL design for modem datapath/PHY blocks, signal processing hardware, Arm compute subsystem, and IO infrastructure, partnering across architecture, verification, and physical design teams to deliver production silicon.
Fra elektronikdesign til færdige robotløsninger Du bliver en del af Mechatronics-teamet i R&D, hvor du samarbejder tæt med specialister inden for elektronik, mekanik og software. Her får du ansvaret for at udvikle…
Designs and verifies next-generation ASICs for SpaceX's Starlink satellite internet system, writing RTL in Verilog/SystemVerilog, defining micro-architecture, and supporting silicon bring-up with cross-disciplinary teams.
Designs and verifies next-generation ASICs for SpaceX's Starlink network, writing RTL in Verilog/SystemVerilog, defining micro-architecture, and supporting timing-clean synthesis and silicon bring-up.
SpaceX seeks a senior RTL design engineer to develop next-generation ASICs for the Starlink satellite constellation, working on architectural trade-offs, Verilog/SystemVerilog implementation, verification, timing closure, and silicon bring-up for space and ground infrastructure.
Designs and verifies next-generation ASICs for Starlink's space and ground infrastructure, defining micro-architecture, writing RTL in Verilog/SystemVerilog, and supporting synthesis, timing closure, and silicon bring-up with cross-functional teams.
Designs digital ASICs and FPGAs for SpaceX's Starshield national-security programs, writing RTL in Verilog/SystemVerilog and taking designs through verification, synthesis/timing closure, and silicon bring-up for space and ground infrastructure.
Designs and verifies next-generation ASICs for Starlink's space and ground infrastructure. Day-to-day work includes block- and system-level digital ASIC verification, test plan development, regression execution, coverage closure, and chip bring-up/validation using UVM and Python.
Verifies digital ASICs at block and system level for SpaceX's Starlink satellites and ground infrastructure, writing test plans, running regressions, and supporting chip bring-up and post-silicon validation using UVM/OVM/VMM and Python.
Verifies digital ASICs at block and system level for SpaceX's Starlink satellites and ground infrastructure. Writes test plans, builds testbenches, runs regressions, closes coverage, and supports chip bring-up and post-silicon validation using UVM/OVM/VMM, Python, and RTL design.
Designs, develops, and tests electronics for Starlink gateways and customer hardware, owning products from concept through production. Works cross-functionally with software, mechanical, RF, and manufacturing teams on schematic capture, PCB layout, bring-up, and debugging using mixed-signal boards, FPGAs, and high-speed interfaces.
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