PCB Designer on SpaceX's Starship team who creates multilayer PCB layouts, places components, routes high-speed digital/analog/RF and power circuits, runs SI/PI simulations, and produces fabrication deliverables while collaborating with hardware engineers using Altium and Xpedition.
Designs and implements next-generation ASICs for Starlink's space and ground infrastructure, performing physical implementation (synthesis, floorplanning, place and route, timing closure, signoff) and building automation scripts while collaborating with cross-disciplinary teams. Core technologies: RTL2GDSII physical design, EDA tools, STA, CMOS/FinFET, and Python/TCL/Perl scripting.
Designs and implements next-generation ASICs for Starlink satellites and ground infrastructure. Day-to-day work includes RTL-to-GDSII physical implementation (floorplanning, place-and-route, timing closure, signoff checks), flow automation, and collaboration with cross-disciplinary ASIC teams using EDA tools and scripting.
Physical Design Engineer developing next-generation ASICs for Starlink satellites and ground infrastructure. Performs RTL2GDSII physical implementation (synthesis, floorplanning, place and route, timing, signoff) and collaborates with cross-functional teams on timing, power, and area targets.
The Physical Security Hardware Specialist installs, maintains, troubleshoots, and repairs physical security hardware—including access control and CCTV systems like Lenel and Avigilon—across SpaceX facilities, while supporting inventory, documentation, and user training.
Installs, maintains, troubleshoots, and repairs physical security hardware such as access control and CCTV systems at SpaceX facilities, working with Lenel and Avigilon platforms and supporting security staff and vendors.
Installs, maintains, troubleshoots, and repairs physical security hardware including CCTV, access control, and intrusion systems across SpaceX facilities. Works with Lenel and Avigilon platforms, manages inventory and work orders, and supports system users and vendors.
As a Platform Engineer on SpaceX's Starlink flight software team, you maintain build systems, code generation tooling, and shared flight software features so satellite and ground engineers can iterate quickly. You work with C/C++, Python, Bazel, and CI/CD tools in Redmond, WA.
Designs, analyzes, and tests DC-DC power converters and electrical power systems for Starmind satellites and orbital AI data centers, collaborating with multidisciplinary teams on high-efficiency power delivery from 1W to kW range in harsh space environments.
Designs, develops, and tests power electronics for Starlink gateways and consumer devices, including AC/DC and DC-DC converters, magnetics, control loops, and PCB layout, working with cross-functional teams from prototype through production ramp.
Power Electronics Engineer designing kV-level power supplies for Starlink gateway TWTA systems, owning full hardware lifecycle from concept to production, using DC-DC converters, magnetics, and high-voltage testing.
Designs and tests DC-DC power converters for Starlink satellites, working on power systems from 1W to kW including solar, battery, and propulsion. Collaborates with multidisciplinary teams to develop hardware for harsh space environments.
Designs and develops power conversion and control systems for Starlink satellites, including DC-DC converters, solar/MPPT, battery, and propulsion systems, working from low voltage to kV range in harsh space environments.
Designs, analyzes, and tests high-reliability DC-DC power converters and power distribution systems for SpaceX's Starship spacecraft, managing electronics development from requirements and schematic capture through prototyping, manufacturing, and test.
Designs and deploys AI capabilities—models, APIs, tools, and integrations—for U.S. federal agencies, working with product, research, infrastructure, and legal teams. Uses Python and frontier AI models to build production-grade SDKs, APIs, and developer tools for government missions.
Designs digital ASICs and FPGAs for SpaceX's Starshield national-security programs, writing RTL in Verilog/System Verilog and taking designs through verification, timing closure, and silicon bring-up for space and ground infrastructure.
Leads a team of cybersecurity engineers defending SpaceX's Starshield satellite network, running red-team exercises, vulnerability discovery, and incident response. Hands-on role blending software and security; requires a Top Secret clearance.
Leads digital ASIC/FPGA design verification for Starlink chips, owning test plans from start to finish and supporting pre-silicon verification through post-silicon validation, using UVM/OVM/VMM methodologies and Python scripting.
Leads digital ASIC and FPGA verification for SpaceX’s next-generation Starlink chips, owning test plans from development through pre-silicon verification, chip bring-up, and post-silicon validation using UVM/OVM/VMM, constrained random verification, and Python scripting.
Principal Design Verification Engineer for SpaceX's Starlink silicon team, leading digital ASIC/FPGA verification at block and system level, developing test plans, coverage models, and performing pre-silicon verification, chip bring-up, and post-silicon validation using UVM, constrained random verification, Python, and RTL design.
Cookies?
A session cookie keeps you signed in. If you accept, we also use analytics cookies (Google Analytics and PostHog) to understand usage. Learn more
We couldn't check your fit for this role — add a CV to your profile to see it next time.