Designs, analyzes, and tests high-power DC-DC converters and electrical power systems for SpaceX’s Starmind satellites and orbital AI data centers, handling magnetics, control loops, and harsh-environment hardware from 1W to many kW.
Designs, analyzes, and tests DC-DC power converters and electrical power systems for Starlink satellites and ground hardware, working with cross-functional teams on power conversion from 1W to kilowatts in harsh environments.
Senior Power Electronics Engineer for Starship who rapidly develops high-reliability rocket and spacecraft electronics, driving DC-DC power converter and power distribution design from requirements and schematic capture through prototyping, bring-up, testing, and manufacturing.
Leads design of kilovolt-level power supplies and DC-DC converters for SpaceX Starlink traveling wave tube amplifiers, owning hardware from concept through production and collaborating with RF, mechanical, and manufacturing teams.
A senior product security engineer at SpaceX designs and builds security infrastructure for Starlink, including cryptographic services and security features for routers, dishes, gateways, and satellites, using software engineering, applied cryptography, and network security skills.
Designs and builds security infrastructure and features for Starlink systems (routers, dishes, gateways, satellites) using Python, C++, and Golang, focused on applied cryptography, network security, and operating system security.
Designs and builds security infrastructure and features for Starlink systems—router, dish, gateways, and satellites—including cryptographic services, using Python, C++, and Golang.
Designs and builds security infrastructure for SpaceX's Starlink satellite internet system, including cryptographic services and security features for routers, dishes, gateways, and satellites. Requires 5+ years of security software development with Python, C++, or Go.
Integrates, tests, and evaluates Starlink Mobile satellite communication network components on satellites and ground stations, ensuring performance and compliance with mobile operator integrations and operating licenses. Works with LTE/5G RAN, EPC/5GC, IMS, and cellular network protocols to support direct-to-handset services.
Leads validation and optimization of SpaceX's 4G/5G RAN software protocol stack for Starlink Mobile, building CI/CD test automation frameworks for eNB/gNB, analyzing UE and base-station logs, and creating data pipelines to improve network KPIs. Core technologies: Python, C/C++, LTE/5G-NR.
The engineer leads validation and optimization of SpaceX's 4G/5G RAN software protocol stack for Starlink Mobile, building CI/CD test automation frameworks and debugging eNB/gNB issues with Python, C/C++, and LTE/5G-NR protocols.
Designs and develops compact RF front-end multi-chip modules for SpaceX's Starlink Mobile network, integrating RFICs, BAW/SAW filters, and printed passives for 5G NR, LTE, and Wi-Fi; performs simulation, lab bring-up, debugging, and production support.
Designs and develops RF front-end multi-chip modules for SpaceX's Starlink Mobile network, integrating RFICs, filters, and passives into compact modules for 5G NR, LTE, and Wi-Fi using simulation, lab testing, and production optimization.
Sr. RFIC Design Engineer designing cutting-edge RF/analog/mixed-signal ICs for Starlink satellite and ground systems, using SiGe/CMOS processes and microwave frequencies (Ku/K/Ka-band).
Sr. RFIC Design Engineer at SpaceX designing next-gen RFICs for Starlink satellite internet, working on SiGe/CMOS circuits at microwave frequencies (Ku/K/Ka-band), simulating with Spectre/ADS/HFSS, and collaborating across systems, firmware, and validation teams.
Designs, simulates, and models RF/analog/mixed-signal integrated circuits for SpaceX's Starlink satellite and ground systems, working with cross-disciplinary teams on next-generation RFICs using SiGe or CMOS processes.
Sr. RFIC Layout Designer at SpaceX working on Starlink satellite internet system, responsible for custom analog/RFIC layout, chip floor planning, DRC/ERC/LVS, and tape-out using advanced process nodes (22nm-5nm) up to 50GHz.
Senior RFIC Layout Designer at SpaceX working on Starlink satellite internet system. Leads custom analog/RF IC layout for advanced nodes (22nm–5nm) up to 50GHz, including floor planning, DRC/ERC/LVS, tape-out, and scripting automation using Skill/Python.
Senior RFIC Layout Designer at SpaceX working on Starlink satellite internet system. Leads custom analog/RF IC layout for advanced nodes (22nm–5nm) up to 50GHz, including floorplanning, DRC/ERC/LVS, tape-out, and scripting automation with Cadence/Skill and Python.
Senior RFIC Layout Designer leading full-chip layout of custom analog and RFIC designs for SpaceX's Starshield national security satellites, including floor planning, DRC/ERC/LVS, tape-out, and advanced node (16nm/7nm/5nm) layouts up to 50GHz.
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