Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads design verification for next-generation connectivity silicon (PCIe, UALink, UCIe) used in rack-scale AI infrastructure. Day to day: builds UVM/SystemVerilog testbenches, defines coverage and test plans, debugs simulations, and partners with RTL, firmware, and post-silicon teams to bring chips to production.
Tech Lead owning internal automation platforms at Astera Labs — building production systems for workflow automation, integrations, identity, and operational data using Python/FastAPI, PostgreSQL, and AI-assisted coding tools.
Leads physical design timing closure for Astera Labs' connectivity ASICs, owning end-to-end static timing analysis (STA) from RTL through sign-off. Works fully on-site in Toronto with RTL, physical design, and verification teams using Cadence/Synopsys tools at TSMC 7nm and below.
A Test Engineer in Aachen, Germany validates semiconductor devices on automated test equipment, troubleshoots hardware/software failures, analyzes yield data, and supports new product qualification using Python, C/C++, or LabVIEW scripting.
Leads a team of physical design engineers in Tel Aviv, driving complex mixed-signal and digital SoCs from RTL handoff through tapeout. Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, and sign-off (STA, IR/EM, DRC, LVS) using tools such as Cadence Innovus, Synopsys PrimeTime/ICC2, and Calibre on advanced-node AI connectivity chips.
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Stellar Jet — це мультидисциплінарне R&D бюро та експериментальне виробництво. Наші проєкти вже довели свою ефективність, і ми продовжуємо активну роботу над перспективними розробками. Зараз ми в пошуку Middle PCB…
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At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our…
About the Role We are looking for a Senior Manager of Package Signal & Power Integrity to lead a small team of engineers delivering SI/PI solutions for next-generation 2.5D/3D chiplet-based products. This is a…
Ideal Candidate Profile The ideal candidate is a technically credible account manager who can build long-term customer relationships while also actively creating new business opportunities. This person does not need to…
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