SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
Sr. RFIC Design Engineer designing cutting-edge RF/analog/mixed-signal ICs for Starlink satellite and ground systems, using SiGe/CMOS processes and microwave frequencies (Ku/K/Ka-band).
Sr. RFIC Design Engineer at SpaceX designing next-gen RFICs for Starlink satellite internet, working on SiGe/CMOS circuits at microwave frequencies (Ku/K/Ka-band), simulating with Spectre/ADS/HFSS, and collaborating across systems, firmware, and validation teams.
Designs, simulates, and models RF/analog/mixed-signal integrated circuits for SpaceX's Starlink satellite and ground systems, working with cross-disciplinary teams on next-generation RFICs using SiGe or CMOS processes.
Develops next-generation Starlink silicon, handling physical implementation from synthesis through signoff (floorplanning, place and route, timing, power/ground grid, physical verification) and improving design flows with automation scripts, working with ASIC teams on timing, power, and area targets. Core technologies: ASIC/SOC RTL2GDSII, EDA tools, STA, Python/TCL/Perl scripting.
Designs and implements next-generation ASIC/SOC silicon for SpaceX's Starlink satellite and ground infrastructure. Day-to-day work includes physical implementation (synthesis, floorplanning, place-and-route, timing, signoff), flow automation, and collaboration with architecture and design teams.
Designs and implements next-generation silicon chips for SpaceX's Starlink network, managing physical design flows from synthesis through signoff using EDA tools and scripting. Collaborates with cross-disciplinary teams on timing, power, area, and physical verification for space and ground infrastructure.
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