SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
Leads digital ASIC/FPGA design verification for Starlink chips, owning test plans from start to finish and supporting pre-silicon verification through post-silicon validation, using UVM/OVM/VMM methodologies and Python scripting.
Leads digital ASIC and FPGA verification for SpaceX’s next-generation Starlink chips, owning test plans from development through pre-silicon verification, chip bring-up, and post-silicon validation using UVM/OVM/VMM, constrained random verification, and Python scripting.
Principal Design Verification Engineer for SpaceX's Starlink silicon team, leading digital ASIC/FPGA verification at block and system level, developing test plans, coverage models, and performing pre-silicon verification, chip bring-up, and post-silicon validation using UVM, constrained random verification, Python, and RTL design.
Designs and verifies next-generation ASICs for Starlink's space and ground infrastructure. Day-to-day work includes block- and system-level digital ASIC verification, test plan development, regression execution, coverage closure, and chip bring-up/validation using UVM and Python.
Verifies digital ASICs at block and system level for SpaceX's Starlink satellites and ground infrastructure, writing test plans, running regressions, and supporting chip bring-up and post-silicon validation using UVM/OVM/VMM and Python.
Verifies digital ASICs at block and system level for SpaceX's Starlink satellites and ground infrastructure. Writes test plans, builds testbenches, runs regressions, closes coverage, and supports chip bring-up and post-silicon validation using UVM/OVM/VMM, Python, and RTL design.
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