Designs, builds, and operates SpaceX’s Starshield data center networks supporting national security missions, including high-speed optical and copper connectivity for 100k+ GPU AI clusters. Collaborates with ML teams on interconnect topology, deploys network hardware, builds automation, and requires Top Secret clearance.
SpaceX Starlink Network Engineer who operates, builds, and deploys global network infrastructure—managing POPs and interconnections, optimizing performance and reliability, troubleshooting strategic customer integrations, and automating network devices—using enterprise/cloud networks, Layer-1 transport, BGP/OSPF/MPLS, Linux, Python, and SDN/NFV.
As a new graduate software engineer on SpaceX's Starlink team, you will develop real-time software, firmware, and deployment infrastructure for satellites, ground stations, and custom hardware. The role uses C, C++, Python, or C# and requires a STEM bachelor's degree and graduation in 2026 or 2027.
Develops reliable, real-time software for SpaceX's Starlink satellite internet system across networking, embedded firmware, infrastructure, and web/mobile platforms; participates in architecture and code reviews and collaborates with cross-functional engineers. Core technologies include C, C++, Python, C#, and networking/distributed systems.
As a new graduate software engineer on SpaceX's Starlink team, you'll develop highly reliable real-time software for satellite internet systems, take part in architecture and code reviews, build prototypes, and collaborate across engineering disciplines. Core technologies: C, C++, Python, C#, UDP/TCP/IP networking, and distributed systems.
Designs and implements software and firmware for SpaceX's next-generation avionics systems, including bring-up, validation, testing, and operational support of flight hardware/software. Core technologies include C/C++, microcontrollers, Linux, and bash scripting.
New graduate software engineer who designs, develops, and tests flight control and simulation software for SpaceX's Starship vehicle, working across application, operating system, networking, firmware, and simulation layers.
As a software engineer on SpaceX's Starship team, you design, develop, and test software that controls and simulates flight systems, working across application, operating-system, networking, firmware, and simulation layers alongside hardware engineers. The role centers on C++, Rust, real-time embedded systems, and distributed computing.
PCB Designer on SpaceX's Starship team who creates multilayer PCB layouts, places components, routes high-speed digital/analog/RF and power circuits, runs SI/PI simulations, and produces fabrication deliverables while collaborating with hardware engineers using Altium and Xpedition.
Designs and implements next-generation ASICs for Starlink's space and ground infrastructure, performing physical implementation (synthesis, floorplanning, place and route, timing closure, signoff) and building automation scripts while collaborating with cross-disciplinary teams. Core technologies: RTL2GDSII physical design, EDA tools, STA, CMOS/FinFET, and Python/TCL/Perl scripting.
Designs and implements next-generation ASICs for Starlink satellites and ground infrastructure. Day-to-day work includes RTL-to-GDSII physical implementation (floorplanning, place-and-route, timing closure, signoff checks), flow automation, and collaboration with cross-disciplinary ASIC teams using EDA tools and scripting.
Physical Design Engineer developing next-generation ASICs for Starlink satellites and ground infrastructure. Performs RTL2GDSII physical implementation (synthesis, floorplanning, place and route, timing, signoff) and collaborates with cross-functional teams on timing, power, and area targets.
Designs, develops, and tests power electronics for Starlink gateways and consumer devices, including AC/DC and DC-DC converters, magnetics, control loops, and PCB layout, working with cross-functional teams from prototype through production ramp.
Leads digital ASIC/FPGA design verification for Starlink chips, owning test plans from start to finish and supporting pre-silicon verification through post-silicon validation, using UVM/OVM/VMM methodologies and Python scripting.
Leads digital ASIC and FPGA verification for SpaceX’s next-generation Starlink chips, owning test plans from development through pre-silicon verification, chip bring-up, and post-silicon validation using UVM/OVM/VMM, constrained random verification, and Python scripting.
Principal Design Verification Engineer for SpaceX's Starlink silicon team, leading digital ASIC/FPGA verification at block and system level, developing test plans, coverage models, and performing pre-silicon verification, chip bring-up, and post-silicon validation using UVM, constrained random verification, Python, and RTL design.
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
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