SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
Designs and verifies next-generation ASICs for SpaceX's Starlink satellite internet system, writing RTL in Verilog/SystemVerilog, defining micro-architecture, and supporting silicon bring-up with cross-disciplinary teams.
Designs and verifies next-generation ASICs for SpaceX's Starlink network, writing RTL in Verilog/SystemVerilog, defining micro-architecture, and supporting timing-clean synthesis and silicon bring-up.
SpaceX seeks a senior RTL design engineer to develop next-generation ASICs for the Starlink satellite constellation, working on architectural trade-offs, Verilog/SystemVerilog implementation, verification, timing closure, and silicon bring-up for space and ground infrastructure.
Designs and verifies next-generation ASICs for Starlink's space and ground infrastructure, defining micro-architecture, writing RTL in Verilog/SystemVerilog, and supporting synthesis, timing closure, and silicon bring-up with cross-functional teams.
Designs and verifies next-generation ASICs for Starlink's space and ground infrastructure. Day-to-day work includes block- and system-level digital ASIC verification, test plan development, regression execution, coverage closure, and chip bring-up/validation using UVM and Python.
Verifies digital ASICs at block and system level for SpaceX's Starlink satellites and ground infrastructure, writing test plans, running regressions, and supporting chip bring-up and post-silicon validation using UVM/OVM/VMM and Python.
Verifies digital ASICs at block and system level for SpaceX's Starlink satellites and ground infrastructure. Writes test plans, builds testbenches, runs regressions, closes coverage, and supports chip bring-up and post-silicon validation using UVM/OVM/VMM, Python, and RTL design.
Designs and validates next-generation ASICs for Starlink's satellite broadband and RF sensing systems. Day-to-day work includes DSP algorithm modeling, digital beamforming and massive MIMO research, link-budget analysis, and collaboration with ASIC/FPGA and RF teams using MATLAB, C/C++, and Python.
Designs and tests next-generation ASICs for Starlink satellite broadband systems, focusing on DSP, digital beamforming, and massive MIMO. Collaborates with cross-functional teams to model RF/wireless modems, generate silicon specifications, and support hardware bring-up and validation.
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