SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
Manages satellite integration build flow and test operations for SpaceX's Starshield program, evaluating designs for manufacturability, interfacing with engineers and technicians, developing assembly procedures, and leading root-cause analysis of non-conformances to ensure mission success.
The Sr. PCB Designer creates PCB layouts for SpaceX's in-house Starshield board designs, partnering with hardware engineers on stackup, placement, routing, libraries, and fabrication documentation using ECAD tools such as Mentor Xpedition and Altium Designer.
A Sr. PCB Designer at SpaceX creates PCB layouts (2–20+ layers) for Starlink hardware such as radio phased arrays and power converters, partnering with hardware engineers on placement, routing, signal/power integrity, and fabrication documentation.
Senior PCB Designer on SpaceX's Starship team responsible for multilayer PCB layout, component placement, high-speed routing, SI/PI simulations, and fabrication deliverables, collaborating with hardware engineers and using tools like Altium and Xpedition.
Designs and develops compact RF front-end multi-chip modules for SpaceX's Starlink Mobile network, integrating RFICs, BAW/SAW filters, and printed passives for 5G NR, LTE, and Wi-Fi; performs simulation, lab bring-up, debugging, and production support.
Designs and develops RF front-end multi-chip modules for SpaceX's Starlink Mobile network, integrating RFICs, filters, and passives into compact modules for 5G NR, LTE, and Wi-Fi using simulation, lab testing, and production optimization.
Sr. RFIC Layout Designer at SpaceX working on Starlink satellite internet system, responsible for custom analog/RFIC layout, chip floor planning, DRC/ERC/LVS, and tape-out using advanced process nodes (22nm-5nm) up to 50GHz.
Senior RFIC Layout Designer at SpaceX working on Starlink satellite internet system. Leads custom analog/RF IC layout for advanced nodes (22nm–5nm) up to 50GHz, including floor planning, DRC/ERC/LVS, tape-out, and scripting automation using Skill/Python.
Senior RFIC Layout Designer at SpaceX working on Starlink satellite internet system. Leads custom analog/RF IC layout for advanced nodes (22nm–5nm) up to 50GHz, including floorplanning, DRC/ERC/LVS, tape-out, and scripting automation with Cadence/Skill and Python.
Senior RFIC Layout Designer leading full-chip layout of custom analog and RFIC designs for SpaceX's Starshield national security satellites, including floor planning, DRC/ERC/LVS, tape-out, and advanced node (16nm/7nm/5nm) layouts up to 50GHz.
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