Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads physical design timing closure for Astera Labs' connectivity ASICs, owning end-to-end static timing analysis (STA) from RTL through sign-off. Works fully on-site in Toronto with RTL, physical design, and verification teams using Cadence/Synopsys tools at TSMC 7nm and below.
Leads a team of physical design engineers in Tel Aviv, driving complex mixed-signal and digital SoCs from RTL handoff through tapeout. Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, and sign-off (STA, IR/EM, DRC, LVS) using tools such as Cadence Innovus, Synopsys PrimeTime/ICC2, and Calibre on advanced-node AI connectivity chips.
Grant Street Group is looking for data conversion developers with strong programming and database skills. If the following describes you, we want to hear from you! You enjoy writing great code. At Grant Street, you…
Description :U970 PARCC (PARIS CARDIOVASCULAR RESEARCH CENTER)Hôpital Européen Georges-Pompidou (HEGP) - 56 rue Leblanc, 75015 ParisAPPRENTI INGÉNIEUR D'ÉTUDES - Administration systèmes, réseaux et sécurité-…
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