SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
Lead and hire a PCB design team for SpaceX's Starshield government satellite and ground systems. Collaborate with engineering, supply chain, and manufacturing to design, route, and document PCBs using tools like Mentor Xpedition and Altium Designer.
Manages a team that designs, verifies, and brings up ASICs and FPGAs for SpaceX's Starshield satellite systems; day-to-day work includes RTL implementation in Verilog/SystemVerilog, architectural trades, timing constraints, EDA-tool flows, and hiring/mentoring engineers.
A PCB Designer at SpaceX creates multilayer PCB layouts (2-20+ layers) for Starlink in-house board designs, including radio phased arrays and solar power converters. They partner with hardware engineers on placement, routing, signal/power integrity, and fabrication documentation using ECAD tools.
Designs and lays out printed circuit boards for SpaceX's Starlink satellites and user terminals, partnering with hardware engineers on component placement, routing (digital, analog, RF, power), library creation, and fabrication documentation using ECAD tools such as Mentor Xpedition and Altium Designer.
Designs and lays out multilayer PCBs (2–20+ layers) for SpaceX's Starlink hardware, partnering with hardware engineers on component placement, high-speed/RF/power routing, design reviews, and fabrication documentation using tools such as Xpedition, Allegro, Altium, or KiCad.
Designs printed circuit board layouts for SpaceX’s Starshield hardware, collaborating with hardware engineers on component placement, routing, and documentation for radio, power, and satellite systems using tools like Mentor Xpedition and Altium.
PCB Designer on SpaceX's Starship team who creates multilayer PCB layouts, places components, routes high-speed digital/analog/RF and power circuits, runs SI/PI simulations, and produces fabrication deliverables while collaborating with hardware engineers using Altium and Xpedition.
Designs digital ASICs and FPGAs for SpaceX's Starshield national-security programs, writing RTL in Verilog/System Verilog and taking designs through verification, timing closure, and silicon bring-up for space and ground infrastructure.
Leads digital ASIC/FPGA design verification for Starlink chips, owning test plans from start to finish and supporting pre-silicon verification through post-silicon validation, using UVM/OVM/VMM methodologies and Python scripting.
Leads digital ASIC and FPGA verification for SpaceX’s next-generation Starlink chips, owning test plans from development through pre-silicon verification, chip bring-up, and post-silicon validation using UVM/OVM/VMM, constrained random verification, and Python scripting.
Principal Design Verification Engineer for SpaceX's Starlink silicon team, leading digital ASIC/FPGA verification at block and system level, developing test plans, coverage models, and performing pre-silicon verification, chip bring-up, and post-silicon validation using UVM, constrained random verification, Python, and RTL design.
Designs and automates RF test infrastructure and capabilities for SpaceX's Starshield satellite communications systems, using Python, C++, and lab equipment such as VNAs and spectrum analyzers while collaborating with hardware and DSP teams.
Designs and brings up custom RF silicon for Starlink satellites, ground gateways, and user terminals by writing low-level C/C++/Python driver libraries, building hardware test platforms, and validating silicon software on physical hardware or FPGA emulators.
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