Verifies NVIDIA's inference accelerator (LPU) ASIC design and implementation, building testbenches and verification infrastructure using SystemVerilog and UVM, and collaborating with architects and design teams to ensure pre- and post-silicon correctness.
Senior ASIC Design Engineer at NVIDIA designing GPU/SoC RTL, performing logic synthesis and timing analysis, integrating modules into SOC, and improving design flows using Perl/Python/C++ scripting.
NVIDIA seeks a Senior ASIC Verification Infrastructure Engineer to build CI, simulation, and pre-submit qualification flows for large ASIC/IP development. The role combines Verilog/SystemVerilog and UVM verification with Python/Perl scripting, root-cause analysis, and automation/metrics across distributed systems, including AI workflows to raise engineering efficiency.
FPGA Verification Engineer for flight-critical avionics on AMD/Xilinx platforms, using UVM/SystemVerilog for coverage-driven verification, DO-254 compliance, and hardware validation.
The engineer designs and runs verification environments for FPGA/ASIC RTL blocks using SystemVerilog, VHDL, and UVM/OVM, creates test plans and coverage tracking, and provides technical leadership on Anduril's Imaging team hardware products.
Designs and runs FPGA/ASIC verification environments and testbenches for RTL blocks using SystemVerilog, VHDL/Verilog and UVM/OVM, tracks coverage, and leads verification for Anduril's defense imaging systems.
Senior FPGA Verification Engineer in Costa Mesa, CA who owns verification of AMD (Xilinx) FPGA/SoC designs for flight-critical avionics, building UVM-based coverage-driven testbenches, SystemVerilog assertions, and regression suites while collaborating on RTL and supporting board bring-up.
The Barkhausen Institut performs research on the latest hardware, software and communication technologies and demonstrates their application in tomorrow’s society. Our goal is to build a flexible and trustworthy IoT…
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
Manages a team that designs, verifies, and brings up ASICs and FPGAs for SpaceX's Starshield satellite systems; day-to-day work includes RTL implementation in Verilog/SystemVerilog, architectural trades, timing constraints, EDA-tool flows, and hiring/mentoring engineers.
Designs and implements next-generation ASICs for Starlink's space and ground infrastructure, performing physical implementation (synthesis, floorplanning, place and route, timing closure, signoff) and building automation scripts while collaborating with cross-disciplinary teams. Core technologies: RTL2GDSII physical design, EDA tools, STA, CMOS/FinFET, and Python/TCL/Perl scripting.
Designs and implements next-generation ASICs for Starlink satellites and ground infrastructure. Day-to-day work includes RTL-to-GDSII physical implementation (floorplanning, place-and-route, timing closure, signoff checks), flow automation, and collaboration with cross-disciplinary ASIC teams using EDA tools and scripting.
Physical Design Engineer developing next-generation ASICs for Starlink satellites and ground infrastructure. Performs RTL2GDSII physical implementation (synthesis, floorplanning, place and route, timing, signoff) and collaborates with cross-functional teams on timing, power, and area targets.
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