What We're Researching We're running a paid study on modern hardware description workflows and RTL implementation. Our goal is to understand how engineers approach automated evaluation and design verification…
NVIDIA seeks a Senior ASIC Verification Infrastructure Engineer to build CI, simulation, and pre-submit qualification flows for large ASIC/IP development. The role combines Verilog/SystemVerilog and UVM verification with Python/Perl scripting, root-cause analysis, and automation/metrics across distributed systems, including AI workflows to raise engineering efficiency.
Fidus is a global high-tech design firm headquartered in Ottawa, with additional design centres in Kitchener-Waterloo and San Jose. We specialize in leading-edge electronic product development, with hardware, embedded…
Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re…
We are currently seeking a Senior Security Research Architect. NVIDIA is seeking a technical leader interesting in a chance to define, craft, , implement, and guide implementation of Trusted Execution Environment…
Develops FPGA/SoC firmware for Anduril’s space systems, handling RTL generation, debug, synthesis, place-and-route, timing closure, and board bring-up while coordinating with internal and external design teams. Core technologies include Xilinx SoC/FPGA (Versal), VHDL/Verilog, Vivado, and high-speed interfaces.
FPGA Design Engineer for Anduril's Air Dominance and Strike team, designing RTL in VHDL/Verilog/SystemVerilog for avionics and mission-critical embedded systems, owning designs from architecture through timing closure and hardware integration.
Leads an electrical engineering team at Anduril Industries to design digital hardware for defense systems, owning FPGA/HDL design cycles and full PCB development (FPGA/SoC/SoM host boards), high-speed digital/compute design reviews, and product schedules.
FPGA Engineer responsible for end-to-end design and verification of FPGA-based software defined radio platforms for electronic warfare, using AMD/Xilinx SOC/FPGA devices, VHDL/Verilog HDL, Linux, and CI/CD in Costa Mesa, CA.
Designs, tests, and implements FPGA hardware using Xilinx SoC/FPGA, writing VHDL/Verilog and performing board bring-up for defense and intelligence systems at Anduril Industries in Reston, Virginia.
Principal Digital Hardware Engineer leading an electrical engineering team to design embedded compute solutions for FPGA/SoC host boards, owning PCB development and FPGA/HDL design workflows at defense tech company Anduril Industries.
Designs and integrates RTL for FPGA and SoC-based avionics and embedded systems, running the full hardware development cycle from architecture and microarchitecture through simulation, synthesis, timing closure, lab bring-up, and system integration, using VHDL/Verilog/SystemVerilog and FPGA toolchains.
Senior Embedded Engineer on Anduril's Imaging team leads FPGA architecture and RTL design (VHDL/Verilog) for new defense imaging product lines, handling hardware/software integration, prototype bring-up, and lab validation using Xilinx Vivado and Intel Quartus.
Develops and maintains production embedded software for electronic warfare platforms, owning Built In Test strategy, fault detection/isolation, and test automation for board-level and RF test stations. Collaborates with manufacturing and test automation engineers on production builds and new product introduction, using typed functional languages (Rust/Haskell) and Linux build infrastructure.
Senior FPGA Engineer owning end-to-end FPGA development and verification for software-defined radio platforms that enable electronic-warfare functions. Works with AMD/Xilinx SoC/FPGAs, VHDL/Verilog DSP, and high-speed interfaces, collaborating with hardware and software teams to bring up boards in Costa Mesa, CA.
Senior FPGA Engineer at Anduril Industries designs, tests, and implements FPGA systems on Xilinx SoC platforms using VHDL/Verilog, working through the full design lifecycle with hands-on board bring-up in Reston, Virginia.
The engineer designs and runs verification environments for FPGA/ASIC RTL blocks using SystemVerilog, VHDL, and UVM/OVM, creates test plans and coverage tracking, and provides technical leadership on Anduril's Imaging team hardware products.
Designs and runs FPGA/ASIC verification environments and testbenches for RTL blocks using SystemVerilog, VHDL/Verilog and UVM/OVM, tracks coverage, and leads verification for Anduril's defense imaging systems.
Leads an electrical engineering team that creates embedded compute solutions for vehicle management, DSP, and networking, owning the full PCB development cycle for FPGA/SoC/SoM host boards and FPGA/HDL design workflows using VHDL/Verilog and Altium Designer.
Senior Mission Software Engineer who owns and drives technical direction for critical areas of Anduril's electronic warfare software stack, architecting and implementing high-performance embedded, backend, deployment, and operator-facing software while mentoring engineers and working directly with customers. Core technologies include Haskell, Rust, C++, Go, TypeScript, Linux, and the Lattice ecosy
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