Senior Verification Engineer (UVM/SystemVerilog)
Posted Updated
We're looking for Senior Verification Engineer to join our client's project
Our requirements
- At least 5 years of verification experience.
- Proven ability to build verification environments from the ground up.
- Experience with UVM and SystemVerilog.
- Strong knowledge of Verification IPs and industry-standard protocols, including PCIe, DDR, and AXI.
Optional
- Understanding of hardware-software interaction.
- Experience with C, C++, Python, or SystemC.