Tech jobs — page 2 · Findyet

177 jobs

Posted Sort

177 jobs Posted Sort

Physical Design Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-time

Designs and implements next-generation ASICs for Starlink's space and ground infrastructure, performing physical implementation (synthesis, floorplanning, place and route, timing closure, signoff) and building automation scripts while collaborating with cross-disciplinary teams. Core technologies: RTL2GDSII physical design, EDA tools, STA, CMOS/FinFET, and Python/TCL/Perl scripting.

Asic Automation Bash Cmos Firmware +4 skills

Physical Design Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-time

Designs and implements next-generation ASICs for Starlink satellites and ground infrastructure. Day-to-day work includes RTL-to-GDSII physical implementation (floorplanning, place-and-route, timing closure, signoff checks), flow automation, and collaboration with cross-disciplinary ASIC teams using EDA tools and scripting.

Asic Automation Bash Cmos Firmware +4 skills

135K – 210K $

Physical Design Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-time

Physical Design Engineer developing next-generation ASICs for Starlink satellites and ground infrastructure. Performs RTL2GDSII physical implementation (synthesis, floorplanning, place and route, timing, signoff) and collaborates with cross-functional teams on timing, power, and area targets.

Asic Automation Bash Cmos Firmware +4 skills

125K – 195K $

Principal ASIC Design Engineer (Starshield)

NewBe an early applicant North AmericaFull-timePrincipal

Designs digital ASICs and FPGAs for SpaceX's Starshield national-security programs, writing RTL in Verilog/System Verilog and taking designs through verification, timing closure, and silicon bring-up for space and ground infrastructure.

Asic FPGA Itar Python Tcl +2 skills

200K – 285K $

RFIC Layout Designer (RFIC Engineering)

NewBe an early applicant North AmericaFull-time

Designs full-chip physical layout for custom RF and analog ICs at SpaceX, partnering with circuit designers on floor planning, power/ground distribution, DRC/ERC/LVS checks, and tape-out to foundries. Core technologies: advanced-node RF/analog layout (to 5nm), EDA tools, Linux, and Perl/Python/shell scripting.

Asic Assembly Bash Firmware Itar +3 skills

115K – 185K $

RFIC Layout Designer (RFIC Engineering)

NewBe an early applicant North AmericaFull-time

Designs physical layouts for custom RF and analog integrated circuits for SpaceX's Starlink silicon projects, handling floor planning, DRC/LVS checks, tape-out, and collaboration with cross-disciplinary IC design teams using EDA tools and Linux.

Asic Assembly Bash Firmware Itar +3 skills

105K – 170K $

RFIC Layout Designer (RFIC Engineering)

NewBe an early applicant North AmericaFull-time

Designs and integrates custom RF and analog IC layouts for SpaceX’s Starlink silicon projects, collaborating with cross-disciplinary teams on floor planning, DRC/ERC/LVS checks, tape-out, and EDA tool evaluation.

Asic Assembly Bash Firmware Itar +3 skills

105K – 175K $

RFIC Layout Designer (Starshield Silicon)

NewBe an early applicant North AmericaFull-time

Designs and integrates custom RF and analog IC layouts for SpaceX's Starshield silicon team, handling floor planning, DRC/LVS/ERC checks, and tape-out for U.S. national security programs.

Asic Assembly Bash Firmware Itar +3 skills

105K – 150K $

Site Reliability Engineer — HPC & Automation (Silicon Engineering)

NewBe an early applicant North AmericaFull-time

Designs, operates, scales, and automates high-performance computing infrastructure for SpaceX’s Silicon Engineering team, supporting chip development for Starlink satellites. Day-to-day work includes managing clusters and services, infrastructure as code, CI/CD pipelines, observability, and automation for silicon simulation workflows.

AI Ansible Ansys API Asic +29 skills

125K – 175K $

Sr. ASIC Design Engineer (Starshield)

NewBe an early applicant North AmericaFull-timeSenior

Designs digital ASICs and FPGAs for SpaceX's Starshield national-security programs, writing RTL in Verilog/SystemVerilog and taking designs through verification, synthesis/timing closure, and silicon bring-up for space and ground infrastructure.

Asic FPGA Itar Python Tcl +2 skills

160K – 225K $

Sr. ASIC Design Verification Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Designs and verifies next-generation ASICs for Starlink's space and ground infrastructure. Day-to-day work includes block- and system-level digital ASIC verification, test plan development, regression execution, coverage closure, and chip bring-up/validation using UVM and Python.

Asic Automation Firmware Itar OOP +3 skills

Sr. ASIC Design Verification Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Verifies digital ASICs at block and system level for SpaceX's Starlink satellites and ground infrastructure, writing test plans, running regressions, and supporting chip bring-up and post-silicon validation using UVM/OVM/VMM and Python.

Asic Automation Firmware Itar OOP +3 skills

165K – 260K $

Sr. ASIC Design Verification Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Verifies digital ASICs at block and system level for SpaceX's Starlink satellites and ground infrastructure. Writes test plans, builds testbenches, runs regressions, closes coverage, and supports chip bring-up and post-silicon validation using UVM/OVM/VMM, Python, and RTL design.

Asic Automation Firmware Itar OOP +3 skills

175K – 280K $

Sr. RFIC Layout Designer (RFIC Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Sr. RFIC Layout Designer at SpaceX working on Starlink satellite internet system, responsible for custom analog/RFIC layout, chip floor planning, DRC/ERC/LVS, and tape-out using advanced process nodes (22nm-5nm) up to 50GHz.

Asic Assembly Bash Firmware Itar +3 skills

140K – 230K $

Sr. RFIC Layout Designer (RFIC Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Senior RFIC Layout Designer at SpaceX working on Starlink satellite internet system. Leads custom analog/RF IC layout for advanced nodes (22nm–5nm) up to 50GHz, including floor planning, DRC/ERC/LVS, tape-out, and scripting automation using Skill/Python.

Asic Assembly Bash Firmware Itar +3 skills

140K – 235K $

Sr. RFIC Layout Designer (RFIC Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Senior RFIC Layout Designer at SpaceX working on Starlink satellite internet system. Leads custom analog/RF IC layout for advanced nodes (22nm–5nm) up to 50GHz, including floorplanning, DRC/ERC/LVS, tape-out, and scripting automation with Cadence/Skill and Python.

Asic Assembly Bash Firmware Itar +3 skills

150K – 245K $

Sr. RFIC Layout Designer (Starshield Silicon)

NewBe an early applicant North AmericaFull-timeSenior

Senior RFIC Layout Designer leading full-chip layout of custom analog and RFIC designs for SpaceX's Starshield national security satellites, including floor planning, DRC/ERC/LVS, tape-out, and advanced node (16nm/7nm/5nm) layouts up to 50GHz.

Asic Assembly Bash Firmware Itar +3 skills

140K – 205K $

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Develops next-generation Starlink silicon, handling physical implementation from synthesis through signoff (floorplanning, place and route, timing, power/ground grid, physical verification) and improving design flows with automation scripts, working with ASIC teams on timing, power, and area targets. Core technologies: ASIC/SOC RTL2GDSII, EDA tools, STA, Python/TCL/Perl scripting.

Asic Automation Bash Cmos Firmware +4 skills

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Designs and implements next-generation ASIC/SOC silicon for SpaceX's Starlink satellite and ground infrastructure. Day-to-day work includes physical implementation (synthesis, floorplanning, place-and-route, timing, signoff), flow automation, and collaboration with architecture and design teams.

Asic Automation Bash Cmos Firmware +4 skills

165K – 260K $

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

NewBe an early applicant North AmericaFull-timeSenior

Designs and implements next-generation silicon chips for SpaceX's Starlink network, managing physical design flows from synthesis through signoff using EDA tools and scripting. Collaborates with cross-disciplinary teams on timing, power, area, and physical verification for space and ground infrastructure.

Asic Automation Bash Cmos Firmware +4 skills

175K – 280K $