Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads a team of physical design engineers in Tel Aviv, driving complex mixed-signal and digital SoCs from RTL handoff through tapeout. Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, and sign-off (STA, IR/EM, DRC, LVS) using tools such as Cadence Innovus, Synopsys PrimeTime/ICC2, and Calibre on advanced-node AI connectivity chips.
Renesas is a global, multi-billion dollar, publicly-traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn,…
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Lead the development of CPU Subsystems (CPUSS), a core component of next-generation microcontrollers. Drive the architecture definition, specification development, design, and verification of CPU subsystem components,…
Engagement: Contract, 40 h/week (full-time) Location: Fully remote; candidates must be based in the EU or UK Start date: Mid-November 2026 Duration: 6 months initially, extension likely English: B2-C1 Interview…
We are looking for an experienced DFT Lead to own end-to-end Design-for-Test activities for complex Automotive MCU/SoC products . The role will drive DFT architecture, implementation, verification, and production-test…
Leads a team of RTL design engineers developing high-performance, low-power IP for Google's Tensor Processing Units (TPUs), driving micro-architecture specifications, design reviews, and cross-functional collaboration on AI/ML hardware acceleration.
FPGA Digital Design Engineer for 6+ month contract at Kepler Communications, developing FPGA code for satellite software-defined radios including DSP algorithms and embedded systems using Xilinx Zynq/UltraScale, Verilog/SystemVerilog, Vivado, and full FPGA design flow.
At Kepler Communications, we're not just imagining the future of on-demand space connectivity - we're leading it! Our mission is to provide real-time on-orbit connectivity for critical missions, enabling a new…
Senior RTL Design Engineer at Delos Data, a startup building foundational technology for AI data center clusters. Designs and implements RTL for complex digital systems using Verilog/SystemVerilog, collaborates across architecture, verification, and physical design teams, and ensures synthesis readiness and timing closure.
Compensation: ₹30,000 – ₹40,000 ASIC Design and Verification Mentor - Front END We are seeking a highly skilled and motivated ASIC Design and Verification Engineer to join our dynamic team. The successful candidate…
About Openchip Openchip is a European Silicon Engineering Company, headquartered in Barcelona, Spain. We aim to democratize the usage of Chips by developing Systems on Chip, SOCs, that combines RISC-V and accelerated…
Mercor is hiring experienced Software and Firmware Engineers to support an advanced engineering and AI research initiative with a leading technology organization. The role requires hands-on engineers who have designed, implemented, integrated, tested, debugged, or validated software and firmware that directly interfaces with real-world hardware systems.
Overview We’re looking for professionals with hands-on, real-world experience in specialized applications. Application Expertise and Access You must already have Vivado installed/available on your own PC running…
Cookies?
A session cookie keeps you signed in. If you accept, we also use analytics cookies (Google Analytics and PostHog) to understand usage. Learn more
We couldn't check your fit for this role — add a CV to your profile to see it next time.