Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads design verification for next-generation connectivity silicon (PCIe, UALink, UCIe) used in rack-scale AI infrastructure. Day to day: builds UVM/SystemVerilog testbenches, defines coverage and test plans, debugs simulations, and partners with RTL, firmware, and post-silicon teams to bring chips to production.
Leads physical design timing closure for Astera Labs' connectivity ASICs, owning end-to-end static timing analysis (STA) from RTL through sign-off. Works fully on-site in Toronto with RTL, physical design, and verification teams using Cadence/Synopsys tools at TSMC 7nm and below.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify…
We are seeking an AMS Verification Engineer to lead verification of the digital content embedded within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership of…
Cookies?
A session cookie keeps you signed in. If you accept, we also use analytics cookies (Google Analytics and PostHog) to understand usage. Learn more
We couldn't check your fit for this role — add a CV to your profile to see it next time.