Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads design verification for next-generation connectivity silicon (PCIe, UALink, UCIe) used in rack-scale AI infrastructure. Day to day: builds UVM/SystemVerilog testbenches, defines coverage and test plans, debugs simulations, and partners with RTL, firmware, and post-silicon teams to bring chips to production.
Leads physical design timing closure for Astera Labs' connectivity ASICs, owning end-to-end static timing analysis (STA) from RTL through sign-off. Works fully on-site in Toronto with RTL, physical design, and verification teams using Cadence/Synopsys tools at TSMC 7nm and below.
Leads a team of physical design engineers in Tel Aviv, driving complex mixed-signal and digital SoCs from RTL handoff through tapeout. Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, and sign-off (STA, IR/EM, DRC, LVS) using tools such as Cadence Innovus, Synopsys PrimeTime/ICC2, and Calibre on advanced-node AI connectivity chips.
Support candidate sourcing through LinkedIn, job boards, and other recruitment channels. Screen resumes and maintain candidate databases. Coordinate interview schedules with candidates and hiring managers. Prepare…
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
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