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Astera Labs

Senior Software Engineer (AI for RTL Design & Formal Verification)

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Summary

Senior Software Engineer building AI-powered tools (LLMs, agentic frameworks) to accelerate RTL design, formal verification, and static/lint checking flows for semiconductor hardware development. Collaborates with hardware teams to integrate AI assistants into CAD/EDA workflows using Python, Verilog/SystemVerilog, and formal verification tools.

  • Design, develop, and deploy AI applications using LLMs, agentic frameworks, and related technologies to support RTL, physical and analog design, static/lint checking, and formal verification flows
  • Build infrastructure to deploy LLM-powered engineering assistants and multi-turn dialogue systems that help designers and verification engineers debug faster and close coverage sooner
  • Develop agentic AI solutions for tasks such as RTL rule and lint checking, RTL optimization, bug triage, formal proof convergence, and static verification report analysis; fine-tune and integrate these solutions with existing CAD/EDA flows
  • Build and maintain design databases and dashboards that combine agentic and deterministic retrieval to surface relevant engineering data and speed up design closure
  • Collaborate closely with RTL design, DV, formal verification, and CAD/EDA teams to understand pain points and translate them into AI-assisted tooling

Benefits

  • Flexible time off in the US
  • Parental leave
  • 401K
  • Retirement and pension plans
  • Competitive medical, dental and vision plans
  • Proficiency in Python for rapid prototyping, with strong fundamentals in data structures, algorithms, and software engineering practices
  • Experience with LLMs, including fine-tuning, building multi-agent systems, RAG pipelines, and vector databases
  • 4-10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint verification, or formal verification methodologies
  • A proactive, self-directed approach to problem-solving and comfort operating with ambiguity
  • Bachelor’s, Master’s degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience
  • Familiarity with RTL design languages (Verilog/SystemVerilog) and formal/static verification tools (e.g., JasperGold, VC Formal, or similar) is strongly preferred
  • Strong analytical, communication, and interpersonal skills, with a proven ability to work effectively in a fast-paced, cross-functional startup environment
  • Direct experience applying AI/ML techniques to EDA or CAD flow problems
  • Proficiency in modern software engineering practices, including version control, testing, and CI/CD
  • Experience with formal property verification, assertion-based verification (SVA), or static timing/lint tools
  • A track record of learning across disparate domains (AI/ML and hardware design) and combining them into novel engineering solutions

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